The present invention relates to semiconductor memory devices that are used as memory devices for cellular phones, personal digital assistants (PDAs), video information processing devices and the like, have nonvolatile memory cells, and are controlled with a plurality of information processing devices.
In electrically reprogrammable nonvolatile semiconductor memory devices, recently, flash memories permitting one-time erasure in a block or chip unit have been adopted in various fields. Such flash memories have two types: NOR flash memories suitable for storing programs, and NAND flash memories suitable for storing data. NOR flash memories feature high-speed random read, while NAND flash memories feature high-speed write/low-speed random read and large capacity.
Taking advantage of the above features, flash memories are applied to equipment in a variety of fields. For example, cellular phones are composed of a baseband section responsible for transmission/reception of waves and signals and an application section responsible for processing of multimedia such as images and music. The baseband section uses NOR flash memories as memories for storing programs for baseband processing. The application section uses both NOR flash memories for storing various programs as in the baseband section and NAND flash memories for storing a large volume of data such as music and images.
Presently, peripheral equipment for these memories, processors and the like is mounted on a separate chip depending on its use, as in a system shown in FIG. 21. In the system of FIG. 21, a memory chip 1 and a CPU 1 are responsible for high-speed random access read operations, while a memory chip 2 and a CPU 2 are responsible for large-volume data rewrite and low-speed random read (normally, serial access read) operations.
Systems including that described above have been asked for cost reduction as a recent trend. In response to this, integration of a plurality of chips is now being sought to reduce the number of components and thus to reduce the cost. Integration of information processing devices such as processors is first being attempted. Memories are yet mounted on separate chips in the conventional manner. With the recent progress in the technologies for smaller size and larger capacity, however, integration of memories of different types is increasingly becoming technically practicable. In future, therefore, integration of memories is desired.
As a technique for integrating memories, it is contemplated that memory arrays of different types such as the NOR type and the NAND type, for example, would be mounted on the same chip as they are.
Conventionally, in some instances, integration of a plurality of memory arrays has been made, as in Japanese Laid-Open Patent Publication No. 2004-273117 (Literature 1). In such instances, a plurality of memory arrays, mounted on the same chip, share a data terminal, an address terminal and a control terminal among them, to permit read operation to be performed during execution of write operation.
In Japanese Laid-Open Patent Publication No. 2003-7052 (Literature 2), also, two memory arrays are mounted on the same chip and share a control circuit therebetween, to permit data to be read from the two memory arrays in synchronization with ‘H’ and ‘L’ periods of a memory sync clock and sent to two memory peripheral devices.
However, the conventional techniques have the following problems. In Literature 1, address and data inputs/outputs (I/Os) are provided individually for the two memory arrays, while write control and read control are shared between the two arrays. Therefore, as shown in FIG. 22, read operation can be executed only after termination of write command input and write data input. More specifically, a write command is decrypted with a system control instruction register in Literature 1 (the period “write command” in FIG. 22), all of write data is captured into a data latch (the period “write data input” in FIG. 22), and then the data is written in a memory array (the period at and after “write start” timing in FIG. 22). Since the write time and erase time of flash memories are slow in general, array peripheral equipment under the write operation is likely to stand idle and thus is ready to execute a mode operable in a short time such as read operation. Therefore, in FIG. 22, after the write start, the system control instruction register in Literature 1 controls the chip to read data from the other memory array (the period “read” in FIG. 22) so as to execute read operation.
As described above, Literature 1 has the problem that during the period of write data input, in which the control circuit is in the write state and data is being written in the data latch, it is unable to cut in and execute read operation.
In Literature 2, also, since the control circuit is shared between the two memory arrays, it is unable to perform read operation during execution of write operation.
In general, besides the problem in Literatures 1 and 2 described above, there is a problem associated with integration of a plurality of memories on one chip. That is, the control terminal, the address terminal and the data terminal are required individually for each of a plurality of processors using the memories, and this multiplies the number of pins required by the number of processors. This increases the memory chip area, blocks the trend toward cost reduction, and also increases power consumption with the increase in the number of pins.
A problem also arises once memories are integrated to give a one-chip memory. In the case that two information processing devices use one memory, competition at accessing the memory that may occur between the two information processing devices must be adjusted. This will increase the burden on the information processing devices for arbitration between the plurality of information processing devices.